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Principle of ICT online test equipment

Publisher: Administrator    Date:2020-04-24

ICT online tester principle summary:
This article introduces the basic knowledge and basic principles of online testing.

1 Summary
1.1 Definition
The ICT online tester, ICT, In-Circuit Test, is a standard test method for inspecting manufacturing defects and component defects by testing the electrical properties and electrical connections of online components. It mainly checks the open and short circuits of individual components and various circuit networks on the line. It has the characteristics of simple operation, fast and fast, and accurate fault location.
The flying probe ICT basically only carries out static testing, the advantage is that no fixture is required, and the program development time is short.
Needle bed ICT can perform analog device function and digital device logic function test, with high fault coverage, but special needle bed fixtures need to be made for each type of board, and the fixture manufacturing and program development cycle is long.

1.2 Scope and characteristics of ICT
Check the electrical performance of the online components on the finished board and the connection of the circuit network. Can quantitatively measure resistance, capacitance, inductance, crystal and other devices, perform functional tests on diodes, transistors, optocouplers, transformers, relays, operational amplifiers, power modules, etc., and perform functional tests on small and medium-sized integrated circuits, such as 74 series, memory type, common drive type, exchange type and other ICs.
It finds defects in manufacturing processes and defects in components by directly testing the electrical performance of online devices. The component class can check the out of tolerance, failure or damage of the component value, and the program error of the Memory class. In the process category, faults such as solder short circuit, wrong component insertion, reverse insertion, missing assembly, pin-up, virtual soldering, PCB short circuit, and wire breakage can be found.
The faults of the test are directly located on specific components, device pins, and network points, and the fault location is accurate. No more professional knowledge is required for repairing the fault. Using program-controlled automated testing, the operation is simple, the test is fast and fast, and the test time of the single board is generally from a few seconds to tens of seconds.

1.3 Significance
Online testing is usually the first test procedure in production, which can reflect the production status in time, which is conducive to process improvement and promotion. The fault board tested by the ICT online tester is easy to maintain due to accurate fault location, which can greatly improve production efficiency and reduce maintenance costs. Because of its specific test items, it is one of the important test methods for modern large-scale production quality assurance.

A brief introduction to ICT test theory
1Basic test method
1.1 Analog device testing
Use an operational amplifier for testing. The concept of "virtual ground" from "A" point is:
∵Ix = Iref
∴Rx = Vs / V0 * Rref
Vs and Rref are the excitation signal source and instrument calculation resistance, respectively. Measure V0, then Rx can be obtained.
If the Rx to be measured is a capacitor or an inductance, then the Vs AC signal source and Rx are in the form of impedance, and C or L can also be obtained.
1.2 Isolation (Guarding)
The above test method is for independent devices, and the devices on the actual circuit are connected to each other and affect each other, so that the Ix must be isolated (Guarding) during testing. Isolation is the basic technique of online testing.
In the upper circuit, due to the connection shunt of R1 and R2, the Ix-ref, Rx = Vs / V0 * Rref equation does not hold. During the test, as long as the points G and F are at the same potential, no current flows through R2, and Ix = Iref remains, and the equation of Rx remains unchanged. Ground point G, because the virtual ground of point F, the two points have the same potential, then isolation can be achieved. In practice, G and F are equipotential through an isolated operational amplifier. The ICT tester can provide many isolation points to eliminate the influence of peripheral circuits on the test.

1.2 Test of IC
For digital ICs, the Vector test is used. Vector test is similar to the truth table measurement, stimulating the input vector, measuring the output vector, and judging the quality of the device through the actual logic function test. Such as: NAND gate test
For analog IC testing, the voltage and current can be excited according to the actual function of the IC, and the corresponding output can be measured as a function block test.
2 Non-vector test
With the development of modern manufacturing technology and the use of very large scale integrated circuits, it often takes a lot of time to write the vector test program of the device. For example, the test program of 80386 takes a skilled programmer nearly half a year. The large number of applications of SMT devices has made the failure phenomenon of the device pin open circuit more prominent. To this end, the company's non-vector testing technology, Teradyne launched MultiScan; GenRad launched Xpress non-vector testing technology.
2.1 DeltaScan analog junction test technology
DeltaScan utilizes the electrostatic discharge protection or parasitic diodes that almost all digital device pins and most mixed signal device pins have to perform simple DC current tests on the independent pin pairs of the device under test. When the power of a certain board is cut off, the equivalent circuit of any two pins on the device.
1 Add a pair of negative voltage to pin A, and the current Ia flows through the forward bias diode of pin A. Measure the current Ia flowing through pin A.
2 Maintain the voltage of pin A, add a higher negative voltage to pin B, and the current Ib flows through the forward bias diode of pin B. Due to the current sharing in the common substrate resistor from pin A and pin B to ground, the current Ia will decrease.
3 Measure the current Ia flowing through pin A again. If Ia has no delta when the voltage is applied to pin B, there must be a connection problem.
The DeltaScan software synthesizes the test results obtained from many possible pin pairs on the device to obtain accurate fault diagnosis. Signal pins, power and ground pins, and substrates all participate in the DeltaScan test, which means that in addition to pin disconnection, DeltaScan can also detect manufacturing failures such as missing devices, reversed insertion, and disconnected bonding wires.
The GenRad type test is called Junction Xpress. It also uses the characteristics of the diode in the IC, but the test is achieved by measuring the spectral characteristics (second harmonic) of the diode. DeltaScan technology does not require additional fixture hardware, becoming the first technology.
2.2 FrameScan capacitance coupling test
FrameScan uses capacitive coupling to detect pin disconnection. Each device has a capacitive probe on it, which stimulates the signal at a certain pin, and the capacitive probe picks up the signal:
1 The multiplexer board on the fixture selects the capacitive probe on a device.
2 The analog test board (ATB) in the tester sends AC signals to each tested pin in turn.
3 The capacitive probe collects and buffers the AC signal on the pin under test.
4 ATB measures the AC signal picked up by the capacitive probe. If a pin is correctly connected to the circuit board, a signal will be detected; if the pin is disconnected, there will be no signal.
The GenRad-like technology is called Open Xpress. The principle is similar.
This technical fixture requires sensors and other hardware, and the test cost is slightly higher.
3 Boundary-Scan boundary scan technology
ICT tester requires at least one test point for each circuit node. However, as device integration increases, functions become stronger, packages become smaller, SMT components increase, the use of multi-layer boards, and PCB board component density increase, it is necessary to put a probe at each node to change It is very difficult to increase the test point and increase the manufacturing cost; at the same time it is difficult to develop a test library for a powerful device and the development cycle is extended. To this end, the Joint Test Organization (JTAG) promulgated the IEEE1149.1 test standard.
IEEE1149.1 defines several important characteristics of a scanning device. First define the four (five) pins that make up the test access port (TAP): TDI, TDO, TCK, TMS, (TRST). Test mode selection (TMS) is used to load control information; secondly, the TAP controller Several different test modes supported, mainly external test (EXTEST), internal test (INTEST), running test (RUNTEST); Finally, Boundary Scan Language (Boundary Scan Description Language), BSDL language describes the important information of scanning devices It defines the pins as input, output and bidirectional types, and defines the TAP mode and instruction set.
Each pin of a device with boundary scan is connected to a serial shift register (SSR) unit, called a scan unit. The scan units are connected together to form a shift register chain, which is used to control and detect the device. foot. Its specific four pins are used to complete the test task.
The scan chains of multiple scan devices are connected together by their TAPs to form a continuous boundary register chain, and the TAP signal is added to the chain head to control and detect the pins of all the devices connected to the chain. This virtual contact replaces the physical contact of the needle bed fixture to each pin of the device, and the virtual access replaces the actual physical access, removing a large number of test pads that occupy PCB board space, reducing the manufacturing cost of PCBs and fixtures.
As a test strategy, when designing the testability of the PCB board, special software can be used to analyze circuit dots and devices with scanning functions to determine how to effectively place a limited number of test points without reducing test coverage. The most economical reduction of test points and test pins.
Boundary scan technology solves the difficulty of not being able to increase test points. More importantly, it provides a simple and quick method to generate test patterns. BSDL files can be converted into test patterns using software tools, such as Teradyne ’s Victory and GenRad Basic Scan and Scan Path Finder. Solve the difficulties of writing complex test libraries.
TAP access port can also realize online programming (In-System Program or On Board Program) such as CPLD, FPGA, Flash Memroy.
4 Nand-Tree
Nand-Tree is a testability design technology invented by Inter. Among our products, only this design is found in the 82371 chip. There is a general procedure * .TR2 file describing its design structure. We can convert this file into a test vector.
The ICT test must have accurate fault location and stable test, which has a lot to do with the circuit and PCB design. In principle, we require that every circuit network point have a test point. After the circuit design has to isolate the state of each device, it can not affect each other. For the design of boundary scan and Nand-Tree, testability requirements should be installed.
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